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| Philips Semiconductors Product Specification Logic level TOPFET PIP3102-R DESCRIPTION Monolithic logic level protected power MOSFET using TOPFET2 technology assembled in a 5 pin surface mounting plastic package. QUICK REFERENCE DATA SYMBOL VDS ID Ptot Tj RDS(ON) SYMBOL VPS PARAMETER Continuous drain source voltage Continuous drain current Total power dissipation Continuous junction temperature Drain-source on-state resistance PARAMETER Protection supply voltage MAX. 50 30 90 150 28 NOM. 5 UNIT V A W C m UNIT V APPLICATIONS General purpose switch for driving lamps motors solenoids heaters FEATURES TrenchMOS output stage with low on-state resistance Separate input pin for higher frequency drive 5 V logic compatible input Separate supply pin for logic and protection circuits with low operating current Overtemperature protection Drain current limiting Short circuit load protection Latched overload trip state reset by the protection pin Diagnostic flag pin indicates protection supply connected, overtemperature condition,overload tripped state, or open circuit load (detected in the off-state) ESD protection on all pins Overvoltage clamping FUNCTIONAL BLOCK DIAGRAM PROTECTION SUPPLY DRAIN FLAG OC LOAD DETECT O/V CLAMP INPUT POWER RIG MOSFET LOGIC AND PROTECTION SOURCE Fig.1. Elements of the TOPFET. PINNING - SOT426 PIN 1 2 3 4 5 mb input flag (connected to mb) protection supply source drain DESCRIPTION PIN CONFIGURATION mb SYMBOL D TOPFET P F I P 3 12 45 S Fig. 2. Fig. 3. October 2002 1 Rev 1.000 Philips Semiconductors Product Specification Logic level TOPFET PIP3102-R LIMITING VALUES Limiting values in accordance with the Absolute Maximum Rating System (IEC 134) SYMBOL VDS ID II IF IP Ptot Tstg Tj Tsold PARAMETER Continuous voltage Drain source voltage1 Continuous currents Drain current Input current Flag current Protection supply current Thermal Total power dissipation Storage temperature Junction temperature2 Mounting base temperature Tmb = 25C continuous during soldering -55 90 175 150 260 W C C C VPS = 5 V; Tmb = 25C VPS = 0 V; Tmb = 85C -5 -5 -5 self limited 30 5 5 5 A A mA mA mA VIS = 0 V 50 V CONDITIONS MIN. MAX. UNIT ESD LIMITING VALUE SYMBOL VC PARAMETER Electrostatic discharge capacitor voltage CONDITIONS Human body model; C = 250 pF; R = 1.5 k MIN. MAX. 2 UNIT kV OVERLOAD PROTECTION LIMITING VALUE With an adequate protection supply connected, TOPFET can protect itself from two types of overload overtemperature and short circuit load. SYMBOL PARAMETER Overload protection3 VDS Drain source voltage For overload conditions an n-MOS transistor turns on between the input and source to quickly discharge the power MOSFET gate capacitance. REQUIRED CONDITION protection supply VPS 4 V 0 35 V The drain current is limited to reduce dissipation in case of short circuit load. Refer to OVERLOAD CHARACTERISTICS. MIN. MAX. UNIT OVERVOLTAGE CLAMPING LIMITING VALUES At a drain source voltage above 50 V the power MOSFET is actively turned on to clamp overvoltage transients. SYMBOL EDSM EDRM PARAMETER Inductive load turn off Non-repetitive clamping energy Repetitive clamping energy CONDITIONS IDM = 20 A; VDD 20 V Tmb = 25C Tmb 95C; f = 250 Hz 350 45 mJ mJ MIN. MAX. UNIT 1 Prior to the onset of overvoltage clamping. For voltages above this value, safe operation is limited by the overvoltage clamping energy. 2 A higher Tj is allowed as an overload condition but at the threshold Tj(TO) the over temperature trip operates to protect the switch. 3 All control logic and protection functions are disabled during conduction of the source drain diode. If the protection circuit was previously latched, it would be reset by this condition. October 2002 2 Rev 1.000 Philips Semiconductors Product Specification Logic level TOPFET PIP3102-R THERMAL CHARACTERISTIC SYMBOL Rth j-mb PARAMETER Thermal resistance Junction to mounting base 1.2 1.39 K/W CONDITIONS MIN. TYP. MAX. UNIT OUTPUT CHARACTERISTICS Limits are for -40C Tmb 150C; typicals are for Tmb = 25C unless otherwise specified. SYMBOL V(CL)DSS IDSS PARAMETER Off-state Drain-source clamping voltage Drain source leakage current On-state RDS(ON) Drain-source resistance 1 CONDITIONS VIS = 0 V ID = 10 mA IDM = 4 A; tp 300 s; 0.01 VPS = 0 V; VDS = 40 V Tmb = 25C MIN. 50 50 - TYP. 60 0.1 21 MAX. 70 70 100 10 50 28 UNIT V V A A m m tp 300 s; 0.01; VPS 4 V IDM = 10 A; VIS 4.4 V Tmb = 25C INPUT CHARACTERISTICS Limits are for -40C Tmb 150C; typicals are for Tmb = 25C unless otherwise specified. SYMBOL VIS(TO) IIS V(CL)IS RIG IISL PARAMETER Normal operation Input threshold voltage2 Input current Input clamping voltage Internal series resistance Input current 3 CONDITIONS ID = 1 mA VIS = 5 V II = 1 mA to gate of power MOSFET VPS 4 V VIS = 5 V MIN. 0.6 1.1 5.5 1 TYP. 1.6 16 6.4 1.7 2.7 MAX. 2.6 2.1 100 8.5 4 UNIT V V A V k mA Tmb = 25C Overload protection latched 1 The drain current required for open circuit load detection is switched off when there is no protection supply, in order to ensure a low off-state quiescent current. Refer to OPEN CIRCUIT LOAD DETECTION CHARACTERISTICS. 2 The measurement method is simplified if VPS = 0 V, in order to distinguish ID from IDSP. Refer to OPEN CIRCUIT LOAD DETECTION CHARACTERISTICS. 3 This is not a directly measurable parameter. October 2002 3 Rev 1.000 Philips Semiconductors Product Specification Logic level TOPFET PIP3102-R PROTECTION SUPPLY CHARACTERISTICS Limits are for -40C Tmb 150C; typicals are for Tmb = 25C. SYMBOL VPSF PARAMETER Protection & detection Threshold voltage1 Normal operation or protection latched Supply current Clamping voltage Overload protection latched VPSR tpr Reset voltage Reset time VPS 1 V 1 10 1.8 45 3 120 V s IF = 100 A; VDS = 5 V 2.5 3.45 4 V A V CONDITIONS MIN. TYP. MAX. UNIT IPS, IPSL V(CL)PS VPS = 4.5 V IP = 1.5 mA 5.5 210 6.5 450 8.5 OPEN CIRCUIT LOAD DETECTION CHARACTERISTICS An open circuit load condition can be detected while the TOPFET is in the off-state. Refer to TRUTH TABLE. VPS = 5 V. Limits are for -40C Tmb 150C and typicals are for Tmb = 25C. SYMBOL IDSP VDSF VISF PARAMETER Off-state drain current 2 3 CONDITIONS VIS = 0 V; 2 V VDS 40 V VIS = 0 V ID = 100 A 4 MIN. 0.9 0.2 0.3 TYP. 1.8 1 0.8 MAX. 2.7 2 1.1 UNIT mA V V Drain threshold voltage Input threshold voltage OVERLOAD CHARACTERISTICS Tmb = 25C unless otherwise specified. SYMBOL ID PARAMETER Short circuit load Drain current limiting Overload protection PD(TO) TDSC Overload power threshold Characteristic time Overtemperature protection Threshold temperature CONDITIONS VPS > 4 V VIS = 5 V; VPS > 4 V device trips if PD > PD(TO) which determines trip time 5 MIN. -40C Tmb 150C 28.5 TYP. 44 MAX. 60 UNIT A 75 250 185 380 250 600 W s Tj(TO) VPS = 5 V from ID 4 A or VDS > 0.2 V 150 170 - C 1 When VPS is less than VPSF the flag pin indicates low protection supply voltage. Refer to TRUTH TABLE. 2 The drain source current which flows in a normal load when the protection supply is high and the input is low. 3 If VDS < VDSF then the flag indicates open circuit load. 4 For open circuit load detection, VIS must be less than VISF. 5 Trip time td sc varies with overload dissipation PD according to the formula td sc TDSC / ln[ PD / PD(TO)]. October 2002 4 Rev 1.000 Philips Semiconductors Product Specification Logic level TOPFET PIP3102-R TRUTH TABLE For normal, open-circuit load and overload conditions or inadequate protection supply voltage. Assumes proper external pull-up for flag pin. Refer to FLAG CHARACTERISTICS. CONDITION Normal on-state Normal off-state Open circuit load Open circuit load Short circuit load1 Over temperature Low protection supply voltage Low protection supply voltage PROTECTION 1 1 1 1 1 1 0 0 KEY `0' equals low `1' equals high `X' equals don't care. INPUT 1 0 1 0 1 X 1 0 FLAG 0 0 0 1 1 1 1 1 OUTPUT ON OFF ON OFF OFF OFF ON OFF FLAG CHARACTERISTICS The flag is an open drain transistor which requires an external pull-up circuit. Limits are for -40C Tmb 150C; typicals are for Tmb = 25C. SYMBOL VFSF IFSF IFSO V(CL)FS RF PARAMETER Flag `low' Flag voltage Flag saturation current Flag `high' Flag leakage current Flag clamping voltage Application information Suitable external pull-up resistance VFF = 5 V 47 k CONDITIONS normal operation; VPS = 5 V IF = 100 A VFS = 5 V overload or fault VFS = 5 V IF = 100 A 5.5 0.1 6.2 10 8.5 A V 0.8 10 1 V mA MIN. TYP. MAX. UNIT SWITCHING CHARACTERISTICS Tmb = 25C; RI = 50 ; RIS = 50 ; VDD = 15 V; resistive load RL = 10 . SYMBOL td on tr td off tf PARAMETER Turn-on delay time Rise time Turn-off delay time Fall time VIS: 5 V 0 V CONDITIONS VIS: 0 V 5 V MIN. TYP. 1.8 3.5 11 5 MAX. 5 8 30 12 UNIT s s s s 1 In this condition the protection circuit is latched. To reset the latch the protection pin must be taken low. Refer to PROTECTION SUPPLY CHARACTERISTICS. October 2002 5 Rev 1.000 Philips Semiconductors Product Specification Logic level TOPFET PIP3102-R CAPACITANCES Tmb = 25 C; f = 1 MHz SYMBOL Ciss Coss Crss Cpso Cfso PARAMETER Input capacitance Output capacitance Reverse transfer capacitance Protection supply pin capacitance Flag pin capacitance CONDITIONS VDS = 25 V; VIS = 0 V VDS = 25 V; VIS = 0 V VDS = 25 V; VIS = 0 V VPS = 5 V VFS = 5 V; VPS = 0 V MIN. TYP. 710 370 26 22 12 MAX. 1050 550 40 UNIT pF pF pF pF pF 120 100 80 PD% Normalise Power Derating 80 70 60 50 ID / A VIS / V = 7 6 5 60 40 20 40 4 30 20 10 3 0 0 20 40 60 80 O 0 100 120 140 0 2 4 6 8 10 12 14 16 Tmb / C VDS / V Fig.4. Normalised limiting power dissipation. PD% = 100PD/PD(25C) = f(Tmb) Fig.6. Typical output characteristics, Tj = 25C. ID = f(VDS); parameter VIS; tp = 300 s & tp < td sc y 40 ID / A 80 70 ID / A VIS / V = 30 60 50 7 6 5 4 3 2 20 40 30 10 20 10 0 0 20 40 60 80 100 120 140 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 2.2 Tmb / C O VDS / V Fig.5. Continuous drain current. ID = f(Tamb); condition: VIS = 5 V Fig.7. Typical on-state characteristics, Tj = 25C. ID = f(VDS); parameter VIS; tp = 300 s October 2002 6 Rev 1.000 Philips Semiconductors Product Specification Logic level TOPFET PIP3102-R 2 1.8 1.6 1.4 1.2 1 0.8 0.6 0.4 0.2 0 a Normalised R DS(ON) = f(T j ) 200 Tj (TO) C Data below 4V is for information only. All spec. values are for normal operation at 4V and above. O 190 180 170 160 150 -50 0 50 100 150 Tj / C O 3 4 5 VPS / V 6 7 8 Fig.8. Normalised drain-source on-state resistance. a = RDS(ON)/RDS(ON)25C = f(Tj); ID = 10 A; VIS = 4.4 V Fig.11. Typical overtemperature protection threshold. Tj(TO) = f(VPS); conditions: VIS = 5 V IDSS / A 50 RDS(ON) / mOhm 100E-6 40 10E-6 max. 30 1E-6 max. typ. 100E-9 typ. 20 10 10E-9 0 0 1 2 3 1E-9 VIS / V 4 5 6 7 8 -50 0 50 100 150 Tj / C O Fig.9. Typical on-state resistance, Tj = 25C. RDS(ON) = f(VIS); conditions: ID = 10 A; VPS = 4 V; tp = 300 s ID / A 80 70 60 50 40 Fig.12. Typical drain source leakage current. IDSS = f(Tj); conditions: VDS = 40 V; VPS = VIS = 0 V IIS / mA y 3.5 VDS = 13V 3.0 2.5 2.0 1.5 30 20 10 0 0 1 2 3 4 5 6 7 8 1.0 Latched Unlatched 0.5 0 0 1 2 3 VIS / V VIS / V 4 5 6 7 Fig.10. Typical transfer characteristics, Tj = 25C. ID = f(VIS); conditions: VPS 4 V tp = 300 s Fig.13. Typical DC input characteristics, Tj = 25C. IIS & IISL = f(VIS); normal operation & protection latched October 2002 7 Rev 1.000 Philips Semiconductors Product Specification Logic level TOPFET PIP3102-R 10E-3 IIS & I ISL 2.5 IDSP / mA IISL 2.0 1E-3 1.5 00E-6 1.0 IDSP is constant from Vds = 2V to 40V IIS 0.5 10E-6 -50 0 50 O Tj / C 100 150 0 0 1 2 VDS / V 3 4 5 Fig.14. Typical DC input currents. IIS & IISL = f(Tj); normal & latched; conditions: VIS = 5 V; VPS = 5 V Fig.17. Off state drain current characteristic. IDSP = f(VDS); conditions: Tj = 25C; VPS = 5 V; VIS = 0 V 3.0 2.5 2.0 1.5 1.0 VIS(TO) / V 2.5 IDSP / mA 2.0 max . 1.5 typ. 1.0 min. 0.5 0.0 -50 0 50 100 O 0.5 150 0 0 1 2 3 Tj / C VPS / V 4 5 6 7 8 Fig.15. Input threshold voltage. VIS(TO) = f(Tj); conditions: ID = 1 mA; VDS = 5 V Fig.18. Off state drain current vs protection supply. IDSP = f(VPS); Tj = 25C; VDS = 13 V; VIS = 0 V 10 8 6 IIS / mA IDSP / mA 2.5 2.0 4 2 0 0 2 VIS / V 1.5 4 6 8 -50 0 50 Tj / C O 100 150 Fig.16. Typical input clamping characteristic. II = f(VIS); normal operation, Tj = 25C Fig.19. Typical off state drain current IDSP = f(Tj); conditions: VDS = 13 V; VPS = 5 V; VIS = 0 V October 2002 8 Rev 1.000 Philips Semiconductors Product Specification Logic level TOPFET PIP3102-R 2 VDSF / V Normal load typ. 3.0 2.8 2.6 2.4 2.2 VPSR / V 1 2.0 Open circuit load 1.8 1.6 1.4 1.2 0 -50 0 50 100 150 1.0 -50 0 50 100 150 Tj / C O Tj / C O Fig.20. Open circuit detection threshold voltage. VDSF = f(Tj); VPS 4 V ; VIS = 0 V Fig.23. Typical protection reset voltage. VPSR = f(Tj); tlr = 100 s VISF / V 1.0 10E-6 IFS / A Normal operation 1E-6 VPS = 0 or 5V max. typ. 0.5 typ. Open circuit detection 00E-9 0 -50 0 50 100 150 10E-9 Tj / C O -50 0 50 O Tj / C 100 150 Fig.21. Open circuit input threshold voltage. VISF = f(Tj); VPS 4 V ; ID = 100 A Fig.24. Typical flag characteristics. IFS = f(Tj); fault & overload operation; VIS = 5 V; VFS = 5 V 2 IPS / mA 4.0 VPSF / V 3.8 3.6 1 3.4 3.2 0 0 1 2 3 3.0 VPS / V 4 5 6 7 8 -50 0 50 Tj / C O 100 150 Fig.22. Typical DC protection supply characteristics. IPS = f(VPS); normal or overload operation; Tj = 25 C Fig.25. Typical protection threshold voltage. VPSF = f(Tj); VDS = 5 V ; IF = 100 A October 2002 9 Rev 1.000 Philips Semiconductors Product Specification Logic level TOPFET PIP3102-R V(CL)DSR VDS VDD 0 ID 0 VIS 0 RI = RIS RF P F I P VII + L VDS D TOPFET VDD RI D TOPFET P F I + VPS -ID/100 VIS P D.U.T. R 01 shunt S RIS S Fig.26. Clamping energy test circuit, RIS = 100 . 2 EDSM = 0.5 LID V(CL)DSR /(V(CL)DSR - VDD ) Fig.29. Test circuit for resistive load switching times. VIS = 5 V VIS & V DS / V VDS 1.2 1.0 EDSM / J 16 14 25 C 0.8 0.6 0.4 0.2 0 0.1 1 O 12 10 8 150 C O 6 4 2 0 VIS L / mH 10 100 0 5 10 15 20 25 30 Time / s 35 40 45 50 Fig.27. Typical non-repetitive clamping energy. EDSM = f(L); conditions: VIS = 0 V Fig.30. Typical switching waveforms, resistive load. RL = 10 ; adjust VDD to obtain ID = 1.5 A; Tj = 25C 4 ID / A 65 VDSS / V ID = 3 4A 2 10mA 1 0 50 VDS / V 60 60 70 -50 0 50 Tj / C O 100 150 Fig.28. Typical clamping characteristic, 25C. ID = f(VDS); conditions: VIS = 0 V; tp 300 s Fig.31. Overvoltage clamping characteristic. VDS = f(Tj); conditions: VIS = 0 V; tp 300 s October 2002 10 Rev 1.000 Philips Semiconductors Product Specification Logic level TOPFET PIP3102-R 80 70 60 ID / A 10000 Capacitance / pF max. 50 40 30 1000 Ciss typ. Coss 100 20 10 0 -50 0 50 min. Crss 100 150 10 0 10 20 Tj / C O VDS / V 30 40 50 Fig.32. Typical overload current, VDS = 5 V. ID = f(Tj); conditions: VIS = 5 V; VPS = 4 V; tp = 300 s Fig.34. Typical capacitances, Ciss, Coss, Crss. C = f(VDS); conditions: VIS = 0 V; f = 1 MHz Zth / ( K / W ) 15 IS / A 1E+01 0.5 1E+00 10 0.2 0.1 0.05 0.02 PD tp D = tp T 1E-01 5 0 T 1E-02 0 0 0.5 1 1E-06 1E-05 1E-04 1E-03 1E-02 1E-01 1E-03 1E+00 1E+01 VSD / V t/s Fig.33. Typical reverse diode current, Tj = 25 C. IS = f(VSDS); conditions: VIS = 0 V; tp = 300 s Fig.35. Transient thermal impedance. Zth j-mb = f(t); parameter D = tp/T October 2002 11 Rev 1.000 Philips Semiconductors Product Specification Logic level TOPFET PIP3102-R MECHANICAL DATA Plastic single-ended surface mounted package (Philips version of D2-PAK); 5 leads (one lead cropped) SOT426 A E A1 D1 mounting base D HD 3 1 Lp 2 4 5 b c Q e e e e 0 2.5 scale 5 mm DIMENSIONS (mm are the original dimensions) UNIT mm A 4.50 4.10 A1 1.40 1.27 b 0.85 0.60 c 0.64 0.46 D max. 11 D1 1.60 1.20 E 10.30 9.70 e 1.70 Lp 2.90 2.10 HD 15.80 14.80 Q 2.60 2.20 OUTLINE VERSION SOT426 REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION ISSUE DATE 98-12-14 99-06-25 Fig.36. SOT426 surface mounting package1, centre pin connected to mounting base. 1 Epoxy meets UL94 V0 at 1/8". Net mass: 1.5 g. For soldering guidelines and SMD footprint design, please refer to Data Handbook SC18. October 2002 12 Rev 1.000 Philips Semiconductors Product Specification Logic level TOPFET PIP3102-R DEFINITIONS DATA SHEET STATUS DATA SHEET STATUS1 Objective data PRODUCT STATUS2 Development DEFINITIONS This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Changes will be communicated according to the Customer Product/Process Change Notification (CPCN) procedure SNW-SQ-650A Preliminary data Qualification Product data Production Limiting values Limiting values are given in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of this specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. Philips Electronics N.V. 2002 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, it is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent or other industrial or intellectual property rights. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices or systems where malfunction of these products can be reasonably expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. 1 Please consult the most recently issued datasheet before initiating or completing a design. 2 The product status of the device(s) described in this datasheet may have changed since this datasheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. October 2002 13 Rev 1.000 |
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